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MYSON TECHNOLOGY
Super On-Screen-Display
FEATURES
* Horizontal sync input may be up to 120 KHz. * On-chip PLL circuitry up to 96 MHz. * Programmable horizontal resolutions up to 1524 dots per display row. * 942 bytes display registers to control full screen display. * Full screen display consists of 15 (rows) by 30 (columns) characters. * 12 x 18 dot matrix per character. * Total 256 characters and graphic fonts including 248 mask ROM fonts and 8 programmable RAM fonts. * 8 color selectable maximum per display character. * Double character height and/or width control. * Programmable positioning for display screen center. * Bordering, shadowing and blinking effect. * Programmable vertical character height (18 to 71 lines) control. * Row to row spacing register to manipulate the constant display height. * 4 programmable background windows with multi-level operation * Software clears for display frame. * Polarity selectable to Hsync and Vsync inputs. * Auto detection for input edge bounce distortion between Hsync and Vsync inputs. * Half tone and fast blanking output. * Software force blank function for external display. * 8 channels 8 bits PWM D/A converters output. * Provide a clock output synchronous to the incoming Hsync for external PWM D/A. * Compatible to SPI bus or I2C interface. * I2C interface with address 7AH (Slave address is mask option). * 16 pins, 20 pins or 24 pins PDIP package.
MTV018
GENERAL DESCRIPTION
MTV018 is designed for monitor applications to display the built-in characters or fonts onto monitor screen. The display operation is by transferring data and control information from micro controller to RAM through a serial data interface. It can execute full screen display automatically and specific functions such as character bordering, shadowing, blinking, double height and width, font by font color control, frame positioning, frame size control by character height and horizontal display resolution, and windowing effect. Moreover, MTV018 also provide 8 PWM DAC channels with 8 bits resolution and a PWM clock output for external digital to analog control.
BLOCK DIAGRAM
SSB 8 DATA SCK DATA 8 VDD LUMAR LUMAG LUMAB BLINK 8 CRADDR
SERIAL DATA INTERFACE
9 ROW, COL ACK CWS CHS
DISPLAY & ROW CONTROL REGISTERS
VSS
SDA DATA 8 ARWDB HDREN VDREN NROW 5 9 9 5 5 RCADDR DADDR FONTADDR WINADDR PWMADDR
VDDA
ADDRESS BUS ADMINISTRATOR
LPN CWS VCLKS
5
CHARACTER ROM USER FONT RAM LUMINANCE & BORDGER GENERATOR
LUMA VSSA BORDER
VFLB VSP CH 7 CHS VERTD 8
VERTICAL DISPLAY CONTROL
5 LPN NROW VDREN
DATA 8 8 VERTD 8 HORD 7 CH
WINDOWS & FRAME CONTROL
BSEN SHADOW OSDENB HSP VSP
HFLB HSP RP HORD 8
HORIZONTAL DISPLAY CONTROL PHASE LOCK LOOP
ARWDB BLANK FBKGC WB WG WR HDREN LUMAR LUMAG LUMAB BLINK VCLKX
ROUT GOUT BOUT FBKG HTONE
VCLKX
COLOUR ENCODER
VCO PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
PWM D/A CONVERTER
8 DATA
POWER ON RESET
PRB
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 1/16 MTV018 Revision 4.0 10/21/1999
MYSON TECHNOLOGY
1.0 PIN CONNECTION
VSSA VCO RP VDDA HFLB SSB SDA SCK
1 2 3 16 15 14
MTV018
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD
VSSA VCO RP VDDA HFLB SSB SDA SCK PWM0 PWM1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6
VSSA VCO RP VDDA HFLB SSB SDA SCK PWM0 PWM1 PWM2 PWM3
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6 PWM5 PWM4
MTV018N
4 5 6 7 8
13 12 11 10 9
MTV018N20
MTV018N24
2.0 PIN DESCRIPTIONS
Name VSSA VCO RP I/O I/O I/O Pin No. N 1 2 3 N20 1 2 3 N24 1 2 3 Descriptions Analog ground. This ground pin is used to internal analog circuitry. Voltage Control Oscillator. This pin is used to control the internal oscillator frequency by DC voltage input from external low pass filter. Bias Resistor. The bias resistor is used to regulate the appropriate bias current for internal oscillator to resonate at specific dot frequency. Analog power supply. Positive 5 V DC supply for internal analog circuitry. And a 0.1uF decoupling capacitor should be connected across to VDDA and VSSA. Horizontal input. This pin is used to input the horizontal synchronizing signal. It is a leading edge triggered and has an internal pull-up resistor. Serial interface enable. It is used to enable the serial data and is also used to select the operation of I2C or SPI bus. If this pin is left floating, I2C bus is enabled, otherwise the SPI bus is enabled. Serial data input. The external data transfer through this pin to internal display registers and control registers. It has an internal pull-up resistor. Serial clock input. The clock-input pin is used to synchronize the data transfer. It has an internal pull-up resistor. Open-Drain PWM D/A converter 0. The output pulse width is programmable by the register of Row 15, Column 19. Open-Drain PWM D/A converter 1. The output pulse width is programmable by the register of Row 15, Column 20.
VDDA
-
4
4
4
HFLB
I
5
5
5
SSB
I
6
6
6
SDA
I
7
7
7
SCK PWM0 PWM1
I O O
8 -
8 9 10
8 9 10
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Name PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 VDD I/O O O O O O O Pin No. N 9 N20 11 12 13 N24 11 12 13 14 15 16 17 Descriptions
MTV018
Open-Drain PWM D/A converter 2. The output pulse width is programmable by the register of Row 15, Column 21. Open-Drain PWM D/A converter 3. The output pulse width is programmable by the register of Row 15, Column 22. Open-Drain PWM D/A converter 4. The output pulse width is programmable by the register of Row 15, Column 23. Open-Drain PWM D/A converter 5. The output pulse width is programmable by the register of Row 15, Column 24. Open-Drain PWM D/A converter 6. The output pulse width is programmable by the register of Row 15, Column 25. Open-Drain PWM D/A converter 7. The output pulse width is programmable by the register of Row 15, Column 26. Digital power supply. Positive 5 V DC supply for internal digital circuitry and a 0.1uF decoupling capacitor should be connected across to VDD and VSS. Vertical input. This pin is used to input the vertical synchronizing signal. It is leading triggered and has an internal pull-up resistor. Half tone output / PWM clock output. This is a multiplexed pin selected by PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B gain of VGA for the transparent windowing effect. Fast Blanking output. It is used to cut off external R, G, B signals of VGA while this chip is displaying characters or windows. Blue color output. It is a blue color video signal output. Green color output. It is a green color video signal output. Red color output. It is a red color video signal output. Digital ground. This ground pin is used to internal digital circuitry.
VFLB HTONE / PWMCK FBKG BOUT GOUT ROUT VSS
I O
10 11
14 15
18 19
O O O O -
12 13 14 15 16
16 17 18 19 20
20 21 22 23 24
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus can be accessed through the serial data interface, one is SPI bus and other is I2C bus. 3.1.1 SPI bus While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV018 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
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SSB
MTV018
SCK
SDA
MS B
first byte last byte
LSB
FIGURE 1. Data transmission protocol There are three transmission formats shown as below: Format (a) R - C - D R - C - D R - C - D Format (b) R - C - D C - D C - D C - D Format (c) R - C - D D D D D D Where R=Row address, C=Column address, D=Display data 3.1.2 I2C bus I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting from writing the slave address 7AH, which is mask option, to MTV018. The protocol is shown in Figure 2.
SCK
SDA
START
B7
B6
first byte
B0
ACK
B7
B0
ACK STOP
@@@@ @ second byte last byte
FIGURE 2. Data transmission protocol (I2C) There are three transmission formats shown as below: Format (a) S - R - C - D R - C - D R - C - D Format (b) S - R - C - D C - D C - D C - D Format (c) S - R - C - D D D D D D Where S=Slave address, R=Row address, C=Column address, D=Display data Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different row address and column address. Format (b) is recommended for updating data that has same row address but different column address. Massive data updating or full screen data change should use format (c) to increase transmission efficiency. The row and column address will be incremented automatically when the format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy data. There are 3 types of data should be accessed through the serial data interface, one is ADDRESS bytes of display registers, second is ATTRIBUTE bytes of display registers and other is user fonts RAM data, the protocol are same for all except the bit6 and bit5 of row address. The MSB(b7) is used to distinguish row and column addresses when transferring data from external controller. The bit6 of row address is used to distinguish display registers and user fonts RAM data and the bit6 of column address is used to differentiate the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". See Table 1.
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TABLE 1. The configuration of transmission formats. Address Row Address Bytes of Display Reg. Columnab Columnc Row Attribute Bytes of Display Reg. Columnab Columnc Row User Fonts RAM Columnab Columnc b7 1 0 0 1 0 0 1 0 0 b6 0 0 1 0 0 1 1 0 1 b5 0 x x 1 x x x C5 C5 b4 x C4 C4 x C4 C4 x C4 C4 b3 R3 C3 C3 R3 C3 C3 x C3 C3 b2 R2 C2 C2 R2 C2 C2 R2 C2 C2 b1 R1 C1 C1 R1 C1 C1 R1 C1 C1 b0 R0 C0 C0 R0 C0 C0 R0 C0 C0
MTV018
Format a,b,c a,b c a,b,c a,b c a,b,c a,b c
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is configured as the state diagram shown in Figure 3 on page 5.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X format (c)
ROW
0, 0
format (b) 0, 0
0, 1
X, X
DAc
FIGURE 3. Transmission state diagram
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external data write in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic increment to address bus when external write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti5/16 MTV018 Revision 4.0 10/21/1999
X, X
COLc
X X,
1 0,
COLab
1, X
DAab
MYSON TECHNOLOGY
MTV018
cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines. The vertical display center for full screen display could be figured out according to the information of vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB, is calculated with the following equation: Vertical delay time = ( VERTD * 4 + 1 ) * H TABLE 2. Repeat line weight of character CH6 - CH0 CH6,CH5=11 CH6,CH5=10 CH6,CH5=0x CH4=1 CH3=1 CH2=1 CH1=1 CH0=1 Repeat Line Weight +18*3 +18*2 +18 +16 +8 +4 +2 +1 Where H = one horizontal line display time
TABLE 3. Repeat line number of character Repeat Line # Repeat Line Weight 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 v +2 v v +4 v v v v +8 v v v v v v v v +16 v v v v v v v v v v v v v v v v +17 v v v v v v v v v v v v v v v v v +18 v v v v v v v v v v v v v v v v v v Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be repeated.
3.4 Horizontal display control
The horizontal display control is used to generate control timing for horizontal display based on double character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calculated with the following equation, Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width Where P = One pixel display time = One horizontal line display time / (HORR*12)
3.5 Phase lock loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution register (HORR). The frequency of VCLK is determined by the following equation:
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VCLK Freq = HFLB Freq * HORR * 12
MTV018
The VCLK frequency ranges from 6MHz to 96MHz selected by (VCO1, VCO0). In addition, when HFLB input is not present to MTV018, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in oscillator to ensure data integrity.
3.6 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register has its corresponding character address on ADDRESS byte, and 1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for row 0 to row 14, it is used to set character size to each respective row. If double width character is chosen, only even column characters could be displayed on screen and the odd column characters will be hidden. ROW # 01 0 1 COLUMN # 28 29 30 31 R E S E R V E D
DISPLAY REGISTERS
ROW CTRL REG
13 14
COLUMN# 02 35 68 911 1218 1926 ROW 15 WINDOW1 WINDOW2 WINDOW3 WINDOW4 FRAME PWM D/A CRTL REG CRTL REG FIGURE 4. Memory map 3.6.1 Register descriptions 1. Display Register, (Row 0 - 14, Column 0 - 29) ADDRESS BYTE b7 b6 MSB
b5
b4 b3 CRADDR
b2
b1
b0 LSB
CRADDR - Define ROM character and user programmable fonts address. (a) 0 ~ 247 248 build-in characters and graphic symbols. (b) 248 ~ 255 8 user programmable fonts. ATTRIBUTE BYTE b7 b6 -
b5 -
b4 -
b3 BLINK
b2 R1
b1 G1
b0 B1
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R1, G1, B1 - These bits are used to specify its relative address character color 1. 2. Row Control Registers, (Row 0 - 14) COLN 30 b7 b6 b5 b4 R2 b3 G2 b2 B2 b1 CHS b0 CWS
MTV018
BLINK - Enable blinking effect while this bit is set to " 1 ". And the blinking is alternate per 32 vertical frames.
R2, G2, B2 - These bits are used to specify its relative row character color 2. While corresponding CCS bit is set to 1, color 2 should be chosen. CHS - Define double height character to the respective row. CWS - Define double width character to the respective row.
3.7 User font RAM
The user font RAM have 288 locations which are allocated between (row 0, column 0) to (row 7, column 35) to specify 8 user programmable fonts, as shown in Figure 5. Each programmable font consists of 12x18 dot matrix. And each row of dot matrix consists of 2 bytes data which include 4 dummy bits as shown in figure 6. That is, the dot matrix data of each font are stored in 36 bytes registers. For example, font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to column 35. etc. COLUMN # 0 1 34 35 36 63
ROW # 0 1
USER FONT RAM
RESERVED
6 7 FIGURE 5. User font RAM memory map
Nth byte leftmost dot of font (N+1)th byte rightmost dot of font
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
12 bits for one row data of font dot matrix Where N=even number
Dummy bits
FIGURE 6. Data format of font dot matrix
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3.8 Character ROM
MTV018
The character ROM contains 248 built-in characters and symbols from address 0 to 247. Each character and symbol consists of 12x18 dots matrix. The detail pattern structures for each character and symbols are shown in "CHARACTERS AND SYMBOLS PATTERN" on page 16.
3.9 Luminance & border generator
There are 2 shift registers included in the design which can shift out of luminance and border dots to color encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with blackedge for right and bottom sides only.
3.10 Window and frame control
The display frame position is completely controlled by the contents of VERTD and HORD. The window size and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure 4. Window 1 has the highest priority, and window 4 is the least, when two windows are overlapping. More detailed information is described as follows: 1. Window control registers, ROW 15 b7 b6 b5 Column ROW START ADDR 0,3,6,OR 9 MSB
b4
b3
b2 b1 ROW END ADDR
b0 LSB
LSB MSB
b7 Column 1,4,7,OR 10 MSB
b6 b5 b4 COL START ADDR
b3 LSB
b2 WEN
b1 CCS
b0 -
b7 Column 2,5,8,OR 11 MSB
b6 b5 b4 COL END ADDR
b3 LSB
b2 R
b1 G
b0 B
START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the start address is greater than the end address, the window will be disabled. WEN - Enable the window display. CCS - When a window is overlapping with the character, character color 2 should be chosen while this bit is set to 1. Otherwise color 1 is selected. R, G, B - Specify the color of the relative background window. 2. Frame control registers, ROW 15 b7 b6 Column 12 MSB
b5
b4 b3 VERTD
b2
b1
b0 LSB
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MTV018
VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each step is 4 Horizontal display lines. The initial value is 4 after power up. HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each step is 6 dots. The initial value is 15 after power up.
Column 14
b7 -
b6 CH6
b5 CH5
b4 CH4
b3 CH3
b2 CH2
b1 CH1
b0 CH0
CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The character vertical height is at least 18 lines if the contents of CH6-CH0 is less than 18. For example, when the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. And if the contents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2 and Table 3 for detail description of this operation. b7 b6 MSB b5 b4 b3 HORR b2 b1 b0 LSB
Column 15
HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is, the pixels' number per H line equal to HORR*12. It is recommended that HORR should be greater than or equal to 36 and smaller than 90M / (Hfreq*12). The initial value is 40 after power up. b7 b6 b5 b4 MSB b3 b2 b1 RSPACE b0 LSB
Column 16
RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will be appended below each display row, and the maximum space is 31 lines. The initial value is 0 after power up. Column 17 b7 OSDEN b6 BSEN b5 SHADOW b4 TRIC b3 BLANK b2 WENCLR b1 RAMCLR b0 FBKGC
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up. BSEN - Enable the bordering and shadowing effect. SHADOW - Activate the shadowing effect if this bit is set, otherwise the bordering is chosen. TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is, while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are in high impedance state. The initial value is 0 after power up. BLANK - Force the FBKG pin output to high while this bit is set to "1". WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after power up. RAMCLR - Clear all ADDRESS bytes of display registers when this bit is set to "1". The initial value is 0 after power up.
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B7 TEST b6 FBKGP b5 PWMCK b4 SELVCL b3 HSP b2 VSP b1 VCO1
MTV018
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the displaying of characters or windows, otherwise, it outputs only during the displaying of characters. Column 18 TEST =0 =1 b0 VCO0
Normal mode. Test mode, not allowed in applications.
FBKGP - Select the polarity of the output pin FBKG =1 Positive polarity FBKG output is selected. =0 Negative polarity FBKG output is selected. The initial value is 1 after power up. PWMCK - Select the output options to HTONE/PWMCK pin. =0 HTONE option is selected. =1 PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB. The frequency is selected by (VCO1, VCO0) shown as Table 4 on page 12. The initial value is 0 after power up. SELVCL - Enable auto detection for horizontal and vertical syncs input edge distorition while the bit is set to "1". The initial value is 0 after power up. HSP = 1 Accept positive polarity Hsync input. = 0 Accept negative polarity Hsync input. = 1 Accept positive polarity Vsync input. = 0 Accept negative polarity Vsync input.
VSP -
VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and horizontal resolution register (HORR). (i) 12K ohm: = (0, 0) 6MHz < Pixel rate < 12MHz = (0, 1) 12MHz < Pixel rate < 24MHz = (1, 0) 24MHz < Pixel rate < 48MHz = (1, 1) 48MHz < Pixel rate < 96MHz (ii) 11K ohm: = (0, 0) 6.5MHz < Pixel rate < 13MHz = (0, 1) 13MHz < Pixel rate < 26MHz = (1, 0) 26MHz < Pixel rate < 52MHz = (1, 1) 52MHz < Pixel rate < 96MHz (iii)10K ohm: = (0, 0) 7MHz < Pixel rate < 14MHz = (0, 1) 14MHz < Pixel rate < 28MHz = (1, 0) 28MHz < Pixel rate < 56MHz = (1, 1) 56MHz < Pixel rate < 96MHz (iv)9.1K ohm: = (0, 0) 7.5MHz < Pixel rate < 15MHz = (0, 1) 15MHz < Pixel rate < 30MHz = (1, 0) 30MHz < Pixel rate < 60MHz = (1, 1) 60MHz < Pixel rate < 96MHz (v)8.2K ohm: = (0, 0) 8MHz < Pixel rate < 16MHz = (0, 1) 16MHz < Pixel rate < 32MHz
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= (1, 0) 32MHz < Pixel rate < 64MHz = (1, 1) 64MHz < Pixel rate < 96MHz (vi)7.5K ohm: = (0, 0) 8.5MHz < Pixel rate < 17MHz = (0, 1) 17MHz < Pixel rate < 34MHz = (1, 0) 34MHz < Pixel rate < 68MHz = (1, 1) 68MHz < Pixel rate < 96MHz (vii)under or equal to 6.2K ohm: = (0, 0) 9.5MHz < Pixel rate < 19MHz = (0, 1) 19MHz < Pixel rate < 38MHz = (1, 0) 38MHz < Pixel rate < 76MHz = (1, 1) 76MHz < Pixel rate < 96MHz where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12 The initial value is (0, 0) after power up. Notes : 1. That is, if HORR is specified, and RP resister = 12K ohm, then (VCO1, VCO0) = (0, 0) if 6000/(HORR * 12) < HFLB Freq (KHz) < 12000/(HORR * 12) = (0, 1) if 12000/(HORR * 12) < HFLB Freq (KHZ) < 24000/(HORR * 12) = (1, 0) if 24000/(HORR * 12) < HFLB Freq (KHZ) < 48000/(HORR * 12) = (1, 1) if 48000/(HORR * 12) < HFLB Freq (KHZ) < 96000/(HORR * 12)
MTV018
2. It is necessary to wait for the PLL to become stable while (i) the HORR register is changed; (ii) the (VCO1, VCO0) bits is changed; (iii) the horizontal signal (HFLB) is changed. 3. When PLL is unstable, don't write data in any address except Column 15,17,18 of Row 15. If data is written in any other address, a malfunction may occur. TABLE 4. PWMCK Frequency and PWMDA sampling rate (VCO1, VCO0) ( 0, 0 ) ( 0, 1 ) ( 1, 0 ) ( 1 ,1 ) PWMCK Freq (6M ~ 12MHz) HFLB Freq * HORR * 12 HFLB Freq * HORR * 6 HFLB Freq * HORR * 3 HFLB Freq * HORR * 3 / 2 PWMDA sampling rate (23K ~ 47KHz) HFLB Freq * HORR * 12 / 256 HFLB Freq * HORR * 6 / 256 HFLB Freq * HORR * 3 / 256 HFLB Freq * HORR * 3 / 512
3.11 PWM D/A converter
There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). These PWM D/A converter outputs pulse width are programmable by writing data to Column 19 to 26 registers of Row 15 with 8-bit resolution to control the pulse width duration from 0/256 to 255/256. And the sampling rate is selected by (VCO1, VCO0) shown as table 4. In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage (5V to 9V) for desired output range. ROW 15 b7 Column 19 | Column 26 MSB b6 b5 b4 b3 PWMDA0 | PWMDA7 b2 b1 b0
LSB
PWMDA0 - PWMDA7 - Define the output pulse width of pin PWM0 to PWM7.
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3.12 Color encoder
MTV018
The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage(VDD,VDDA) Voltage with respect to Ground Storage Temperature Ambient Operating Temperature -0.3 to +7 V -0.3 to VDD+0.3 V -65 to +150 oC 0 to +70 oC
5.0 OPERATING CONDITIONS
DC Supply Voltage(VDD,VDDA) Operating Temperature +4.75 to +5.25 V 0 to +70 oC
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
Symbol VIH VIL VOH VOL VODH Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Open Drain Output High Voltage Open Drain Output Low Voltage Standby Current Operating Current Conditions (Notes) IOH -5 mA IOL 5 mA (For all OD pins, and pulled up by external 5 to 9V power supply) 5 mA IDOL ( For all OD pins ) Vin = VDD, Iload = 0uA Pixel rate=96MHz Iload = 0uA Min. 0.7 * VDD VSS-0.3 VDD-0.8 5 Max. VDD+0.3 0.3 * VDD (0.2 * VDD for SSB pin) 0.5 9 Units V V V V V
VODL ISB ICC
-
0.5 12 20
V mA mA
7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)
Symbol fHFLB Tr Tf Parameter HFLB input frequency Output rise time Output fall time Min. 15 Typ. Max. 120 5 5 Units KHz ns ns
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MTV018 Revision 4.0 10/21/1999
MYSON TECHNOLOGY
MTV018
Symbol tBCSU tBCH tDCSU tDCH tSCKH tSCKL tSU:STA tHD:STA tSU:STO tHD:STO
Parameter SSB to SCK set up time SSB to SCK hold time SDA to SCK set up time SDA to SCK hold time SCK high time SCK low time START condition setup time START condition hold time STOP condition setup time STOP condition hold time
Min. 200 100 200 100 500 500 500 500 500 500
Typ. -
Max. -
Units ns ns ns ns ns ns ns ns ns ns
8.0 TIMING DIAGRAMS
tSCKH
SCK
tSCKL
SSB
tBCSU tBCH
SDA
tDCSU tDCH
FIGURE 7. Data interface timing(SPI)
t SCKH
SCK
t SU:STA t SCKL t HD:STO
SDA
t HD:STA t DCSU t DCH t SU:STO
FIGURE 8. Data interface timing(I2C)
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MTV018 Revision 4.0 10/21/1999
MYSON TECHNOLOGY
9.0 PACKAGE DEMENSION
9.1 16 Pin 300mil
R10Max (4X ) 55 +/-20 R40 250 +/-4 90 +/-20
MTV018
312 +/-12
350 +/-20
75 +/-20 90 +/-20 750 +/-10 15 Max 7 Typ
65 +/-4 55 +/-4 310Max
10
35 +/-5
115 Min 15 Min 100Ty p 18 +/2Typ 60 +/5Typ
9.2 20 pin 300mil
312 +/-12 55 +/-20 R40 250 +/-4
R10Max (4X ) 90 +/-20 350 +/-20
75 +/-20 90 +/-20 1020 +/-10 15 Max 7 Typ
65 +/-4 55 +/-4 310Max
10
35 +/-5 115 Min 15 Min 100Typ 18 +/-2Typ 60 +/-5Typ
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MTV018 Revision 4.0 10/21/1999
MYSON TECHNOLOGY
9.3 24 Pin 300mil
R10Max (4X)
MTV018
312+/-12
80+/-20
350+/-20 250+/-4
R40
55+/-20
930+/-10 1245+/-10 15Max 7Ty p 35+/-5
10 65+/-4 65+/-4
115Min
15Min. 100Ty p 18+/2Typ 60+/5Typ
10.0 CHARACTERS AND SYMBOLS PATTERN
Please see the attachment.
Myson Technology, Inc. http://www.myson.com.tw No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. Tel: 886-3-5784866 Fax: 886-3-5785002
Myson Technology USA, Inc. http://www.myson.com 20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A. Tel:408-252-8788 FAX: 408-252-8789 Sales@myson.com
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MTV018 Revision 4.0 10/21/1999

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